<code>


-- data_input( * ) indices are the register numbers

-- All diff_bus_* signals are 1-to-1 in-to-out

-- An attempt is made to indicate all outputs driven by inputs from another bank ; probably incomplete

-- Except as noted, each output signal (may be 2 io's) is driven by one input signal (may be 2 io's)


        data_input(   0  )  <=   DIFF_map_out(  5 )  ;  -- Bank 18
        data_input(   1  )  <=   DIFF_map_out( 10 )  ;
        data_input(   2  )  <=   DIFF_map_out( 15 )  ;
        data_input(   3  )  <=   SNGL_bus(      7 )  ;
        data_input(   4  )  <=   SNGL_bus(      6 )  ;
        data_input(   5  )  <=   SNGL_bus(     23 )  ;
        data_input(   6  )  <=   SNGL_bus(     24 )  ;
        data_input(   7  )  <=   SNGL_bus(    111 )  ;
        data_input(   8  )  <=   SNGL_bus(    112 )  ;
        data_input(   9  )  <=   SNGL_bus(    109 )  ;
        data_input(  10  )  <=   SNGL_bus(    110 )  ;
        data_input(  11  )  <=   SNGL_bus(    107 )  ;
        data_input(  12  )  <=   SNGL_bus(    108 )  ;
        data_input(  13  )  <=   SNGL_bus(    131 )  ;
        data_input(  14  )  <=   SNGL_bus(    106 )  ;
        data_input(  15  )  <=   DIFF_map_out( 14 )  ;  -- Bank 17

        data_input(  16  )  <=   DIFF_map_out( 19 )  ;            
        data_input(  17  )  <=   DIFF_map_out(  1 )  ;            
        data_input(  18  )  <=   SNGL_bus(     21 )  ;
        data_input(  19  )  <=   SNGL_bus(     22 )  ;
        data_input(  20  )  <=   SNGL_bus(     12 )  ;
        data_input(  21  )  <=   SNGL_bus(     13 )  ;
        data_input(  22  )  <=   SNGL_bus(     10 )  ;
        data_input(  23  )  <=   SNGL_bus(     41 )  ;
        data_input(  24  )  <=   SNGL_bus(      4 )  ;
        data_input(  25  )  <=   SNGL_bus(      5 )  ;
        data_input(  26  )  <=   SNGL_bus(      0 )  ;
        data_input(  27  )  <=   SNGL_bus(      1 )  ;
        data_input(  28  )  <=   SNGL_bus(     14 )  ;
        data_input(  29  )  <=   SNGL_bus(     15 )  ;
        data_input(  30  )  <=   DIFF_map_out( 12 )  ;  -- Bank 38
        data_input(  31  )  <=   DIFF_map_out( 17 )  ;

        data_input(  32  )  <=   DIFF_map_out(  9 )  ;  -- Bank 16
        data_input(  33  )  <=   SNGL_bus(     80 )  ;  -- Input from Bank 17
        data_input(  34  )  <=   SNGL_bus(     85 )  ;  -- Input from Bank 17
        data_input(  35  )  <=   SNGL_bus(     68 )  ;  -- Input from Bank 17
        data_input(  36  )  <=   SNGL_bus(     69 )  ;  -- Input from Bank 17
        data_input(  37  )  <=   SNGL_bus(     56 )  ;  -- Input from Bank 17
        data_input(  38  )  <=   SNGL_bus(     57 )  ;  -- Input from Bank 17
        data_input(  39  )  <=   SNGL_bus(    139 )  ;
        data_input(  40  )  <=   SNGL_bus(     39 )  ;
        data_input(  41  )  <=   SNGL_bus(     30 )  ;
        data_input(  42  )  <=   SNGL_bus(     33 )  ;
        data_input(  43  )  <=   SNGL_bus(     28 )  ;
        data_input(  44  )  <=   SNGL_bus(     29 )  ;
        data_input(  45  )  <=   DIFF_map_out( 18 )  ;  -- Bank 13
        data_input(  46  )  <=   SNGL_bus(    102 )  ;  -- Input from Bank 16
        data_input(  47  )  <=   SNGL_bus(    101 )  ;  -- Input from Bank 16

        data_input(  48  )  <=   SNGL_bus(    100 )  ;  -- Input from Bank 16
        data_input(  49  )  <=   SNGL_bus(    103 )  ;
        data_input(  50  )  <=   SNGL_bus(     99 )  ;
        data_input(  51  )  <=   SNGL_bus(     88 )  ;
        data_input(  52  )  <=   SNGL_bus(     97 )  ;
        data_input(  53  )  <=   SNGL_bus(     98 )  ;
        data_input(  54  )  <=   SNGL_bus(     90 )  ;
        data_input(  55  )  <=   SNGL_bus(     96 )  ;
        data_input(  56  )  <=   SNGL_bus(     94 )  ;
        data_input(  57  )  <=   SNGL_bus(     95 )  ;
        data_input(  58  )  <=   DIFF_map_out( 20 )  ;  -- Bank 35
        data_input(  59  )  <=   DIFF_map_out(  2 )  ;
        data_input(  60  )  <=   SNGL_bus(    116 )  ;
        data_input(  61  )  <=   SNGL_bus(     34 )  ;
        data_input(  62  )  <=   SNGL_map_out(  9 )  ;  -- Differential sngl_bus driven by single-ended tmv_*bus
        data_input(  63  )  <=   SNGL_map_out( 10 )  ;  -- Differential sngl_bus driven by single-ended tmv_*bus

        data_input(  64  )  <=   DIFF_map_out(  3 )  ;  -- Bank 12
        data_input(  65  )  <=   sngl_bus(     55 )  ;  -- Input from Bank 13
        data_input(  66  )  <=   sngl_bus(     47 )  ;  -- Input from Bank 13
        data_input(  67  )  <=   sngl_bus(     43 )  ;  -- Input from Bank 13
        data_input(  68  )  <=   sngl_bus(     44 )  ;
        data_input(  69  )  <=   sngl_bus(     45 )  ;
        data_input(  70  )  <=   sngl_bus(     83 )  ;
        data_input(  71  )  <=   sngl_bus(     53 )  ;
        data_input(  72  )  <=   sngl_bus(     54 )  ;
        data_input(  73  )  <=   sngl_bus(     48 )  ;
        data_input(  74  )  <=   sngl_bus(     49 )  ;  -- Input from Bank 11
        data_input(  75  )  <=   sngl_bus(    119 )  ;  -- Input from Bank 11
        data_input(  76  )  <=   sngl_bus(    121 )  ;  -- Input from Bank 11
        data_input(  77  )  <=   DIFF_map_out( 13 )  ;  -- Bank 11
        data_input(  78  )  <=   sngl_bus(     72 )  ;
        data_input(  79  )  <=   sngl_bus(     73 )  ;

        data_input(  80  )  <=   sngl_bus(     64 )  ;
        data_input(  81  )  <=   sngl_bus(     65 )  ;
        data_input(  82  )  <=   sngl_bus(     89 )  ;
        data_input(  83  )  <=   sngl_bus(     84 )  ;
        data_input(  84  )  <=   sngl_bus(     50 )  ;
        data_input(  85  )  <=   sngl_bus(     93 )  ;
        data_input(  86  )  <=   sngl_bus(     46 )  ;
        data_input(  87  )  <=   sngl_bus(    115 )  ;  -- Input from Bank 10
        data_input(  88  )  <=   sngl_bus(    104 )  ;  -- Input from Bank 10
        data_input(  89  )  <=   sngl_bus(    105 )  ;  -- Input from Bank 10
        data_input(  90  )  <=   DIFF_map_out(  6 )  ;  -- Bank 36
        data_input(  91  )  <=   DIFF_map_out( 11 )  ;
        data_input(  92  )  <=   SNGL_map_out(  6 )  ;  -- Differential sngl_bus driven by single-ended tmv_*bus
        data_input(  93  )  <=   SNGL_map_out(  7 )  ;  -- Differential sngl_bus driven by single-ended tmv_*bus
        data_input(  94  )  <=   SNGL_map_out(  8 )  ;  -- Differential sngl_bus driven by single-ended tmv_*bus
        data_input(  95  )  <=   sngl_bus(      9 )  ;  -- Input from Bank 35

        -- The last 16-bit register in Bank 36 ends up in the 4th column

        data_input(  96  )  <=   sngl_bus(      8 )  ;  -- Input from Bank 35  -- still in Bank 36
        data_input(  97  )  <=   SNGL_bus(     25 )  ;  -- Input from Bank 35  -- Bank 32
        data_input(  98  )  <=   DIFF_map_out(  8 )  ;  -- Bank 10
        data_input(  99  )  <=   sngl_bus(     81 )  ;
        data_input( 100  )  <=   sngl_bus(     82 )  ;
        data_input( 101  )  <=   sngl_bus(     76 )  ;
        data_input( 102  )  <=   sngl_bus(     77 )  ;
        data_input( 103  )  <=   sngl_bus(     70 )  ;
        data_input( 104  )  <=   sngl_bus(     71 )  ;
        data_input( 105  )  <=   sngl_bus(     62 )  ;
        data_input( 106  )  <=   sngl_bus(     63 )  ;
        data_input( 107  )  <=   sngl_bus(     58 )  ;  -- Expected fail ; AND of 6 failing tmv_*bus inputs ; 43 on 2nd screen
        data_input( 108  )  <=   sngl_bus(     59 )  ;
        data_input( 109  )  <=   sngl_bus(     51 )  ;
        data_input( 110  )  <=   sngl_bus(     52 )  ;
        data_input( 111  )  <=   dut_gen_clk_outd    ;  -- AND of 3 clocks signals, not all in Bank 10

        data_input( 112  )  <=   DIFF_map_out( 16 )  ;  -- Bank 37
        data_input( 113  )  <=   DIFF_map_out(  7 )  ;            
        data_input( 114  )  <=   SNGL_map_out(  0 )  ;  -- Differential sngl_bus driven by differential diff_clka
        data_input( 115  )  <=   SNGL_map_out(  1 )  ;  -- Differential sngl_bus driven by single-ended tmv_*bus
        data_input( 116  )  <=   SNGL_map_out(  2 )  ;  -- Differential sngl_bus driven by single-ended tmv_*bus
        data_input( 117  )  <=   SNGL_map_out(  3 )  ;  -- Differential sngl_bus driven by single-ended tmv_*bus
        data_input( 118  )  <=   SNGL_map_out(  4 )  ;  -- Differential sngl_bus driven by single-ended tmv_*bus
        data_input( 119  )  <=   SNGL_map_out(  5 )  ;  -- Differential sngl_bus driven by single-ended tmv_*bus
        data_input( 120  )  <=   DIFF_map_out(  0 )  ;  -- Bank 30
        data_input( 121  )  <=   DIFF_map_out(  4 )  ;            
        data_input( 122  )  <=   SNGL_map_out( 11 )  ;  -- Differential sngl_bus driven by single-ended tmv_*bus
        data_input( 123  )  <=   SNGL_map_out( 12 )  ;  -- Differential sngl_bus driven by single-ended tmv_*bus
        data_input( 124  )  <=   SNGL_map_out( 13 )  ;  -- Differential sngl_bus driven by single-ended tmv_*bus
        data_input( 125  )  <=   SNGL_map_out( 14 )  ;  -- Differential sngl_bus driven by single-ended tmv_*bus
        data_input( 126  )  <=   SNGL_map_out( 15 )  ;  -- Differential sngl_bus driven by single-ended tmv_*bus
        data_input( 127  )  <=   SNGL_map_out( 16 )  ;  -- Differential sngl_bus driven by single-ended tmv_*bus




</code>